1. Field of the Invention
The present invention relates to semiconductor integrated circuit manufacturing and, more particularly to a method of forming side spacers, particularly on space-defined double patterning (SDDP).
2. Description of the Related Art
Photolithography technology has recently faced difficulty of forming patterns having pitches smaller than the submicron level. Various approaches have been studied, and one of the promising methods is space-defined double patterning (SDDP) which makes it possible to create narrow pitches beyond limitations of conventional lithography such as light source wavelength and high index immersion fluid. Generally, SDDP needs one conformal spacer film and hardmask template wherein the conformal spacer film is deposited on the template normally having convex patterns. A silicon oxide layer is commonly used as a conformal spacer, and a hardmask template is typically constituted by photoresist (PR) prepared by a spin-on or CVD process.
As discussed below, the present inventors have recognized several problems in SDDP and developed solutions thereto, which solutions can also be applicable to general patterning processes. Thus, the present invention relates to improvement on general patterning processes using a hardmask, and particularly on SDDP.
Any discussion of problems and solutions involved in the related art has been included in this disclosure solely for the purposes of providing a context for the present invention, and it should not be taken as an admission that any or all of the discussion were known at the time the invention was made.
In SDDP process flow, a photoresist pattern 12 is formed on a substrate 11 as shown in FIG. 1(a). When etching a photoresist layer to form the photoresist pattern, each formed photoresist protrusion 12 has a widened footing portion at its bottom, and thus, the distance between the formed photoresist protrusions at their bottoms (W′) is shorter than that their side walls (W). When depositing a spacer layer 13 such as a SiO layer by plasma enhanced atomic layer deposition (PE-ALD) over the photoresist pattern as shown in FIG. 1(b), the spacer layer 13 deposits along the surface of the photoresist pattern having the widened footing portions. When the spacer layer is etched by, e.g., reactive ion etching (RIE) to remove the top and bottom to form side spacers 14 as shown in FIG. 1(c), the widened footings of the photoresist pattern are transferred to the side spacers 14. As a result, the thickness of the side spacer at the bottom appears to be widened (F), which is significantly greater than the thickness of the side spacer itself, thereby causing unexpected critical dimension (CD) changes or the like.
In order to achieve patterning smaller than the resolution limit by, e.g., SDDP, many photoresist trimming techniques such as trimming by plasma have been reported. However, it is still difficult to control the transferred footing shape. For example, by using an underlying layer having an increased etch rate, while trimming a photoresist layer, a mask pattern is formed in the underlying layer (e.g., JP 2004-310019). However, by using a combination of an underlying layer and a photoresist layer, even if the footing of the etched photoresist can be smaller while trimming the etched photoresist, a footing shape is transferred to and formed in the underlying layer. Thus, the footing problem is not solved. FIG. 2 shows this problem. When a photoresist layer which is formed on an underlying layer 21 formed on a substrate 24 is etched, a widened footing is formed in the etched photoresist 22 as shown in FIG. 2(a). While trimming the etched photoresist 22 isotropically (FIG. 2(b)), the widened footing of the etched photoresist is smaller. However, the footing of the etched photoresist is transferred to the underlying layer as shown in FIG. 2(c).